Liquid crystal display devices which are used in various fields including small-sized mobile phones and large-sized television exceeding 30 inches are formed from a thin film transistor (hereinafter referred to as “TFT”) as a switching element; a transparent conductive film (oxide conductive film) constituting a pixel electrode; an interconnection part such as a gate interconnection and a source-drain interconnection; a TFT substrate including an Si semiconductor layer such as amorphous silicon (a-Si) and polycrystalline silicon (p-Si); a counter substrate which is disposed opposing the TFT substrate at a prescribed distance and includes a common electrode; and a liquid crystal layer filled between the TFT substrate and the counter substrate.
At present, as described above, a-Si is frequently used for the semiconductor layer of TFT for liquid crystal. But, next-generation displays are required to achieve large size, high resolution and high-speed driving. The conventional a-Si is low in carrier mobility, so that it is unable to satisfy such requirement specs. Then, in recent years, attention is paid to oxide semiconductors. The oxide semiconductors have a high carrier mobility as compared with a-Si. Furthermore, the oxide semiconductors can be formed with a large area at a low temperature by the sputtering method, and therefore, resin substrates having low heat resistance and the like can also be used. As a result, it is possible to realize a flexible display.
As an example of using such an oxide semiconductor for a semiconductor device, for example, in Patent Document 1, one obtained by using any one of zinc oxide (ZnO), cadmium oxide (CdO), and a compound or mixture of zinc oxide (ZnO) to which a IIB element, a IIA element or a VIB element is added, and doping with a 3d transition metal element, a rare earth element or an impurity capable of making the resistance high without losing transparency of the transparent semiconductor is used. Of the oxide semiconductors, oxides containing at least one or more elements selected from the group consisting of In, Ga, Zn, and Sn (e.g., IGZO, ZTO, IZO, ITO, ZnO, AZTO, GZTO) have a very high carrier mobility, and therefore, they are preferably used.
In display devices represented by liquid crystal display devices and the like, as interconnection materials of gate interconnections, source-drain interconnections or the like, pure Al or an Al-based alloy such as A—Nd, which is relatively small in electrical resistance and is easy for micromachining, is frequently used. But, with the progress of increase in size and high image quality of the display device, problems to be caused due to large interconnection resistance, such as signal delay and power loss, have been actualized. For that reason, copper (Cu) having lower resistance than Al is paid attention as the interconnection material. An electrical resistivity of an Al thin film is 3.0×10−6Ω·cm, whereas an electrical resistivity of a Cu thin film is low as 2.0×10−6Ω·cm.
But, Cu involves a problem that its adhesion to a glass substrate or an insulating film to be deposited thereon (a gate insulating film, etc.) is low, so that it peels off. Also, since Cu is low in adhesion to a glass substrate or the like, there is a problem that it is difficult to achieve wet etching or dry etching for processing into an interconnection shape. Then, there are proposed various technologies for enhancing the adhesion of Cu to a glass substrate.
For example, Patent Documents 2 to 4 disclose technologies for contriving to enhance the adhesion by allowing a layer of a high melting point metal such as molybdenum (Mo) and chromium (Cr) to intervene between the Cu interconnection and the glass substrate. But, according to such technologies, steps of depositing the high melting point metal layer increase, and manufacturing costs of a display device increase. Furthermore, in view of the fact that different metals, Cu and the high melting point metal (Mo, etc.), are laminated, there is a concern that corrosion is caused at an interface between Cu and the high melting point metal during the wet etching. Also, in such different metals, a difference in an etching rate is caused, and therefore, there may be a caused problem that an interconnection cross section cannot be formed into a desired shape (for example, a shape with a taper angle of from about 45 to 60°). Furthermore, an electrical resistivity of a high melting point metal, for example, that of Cr (about 15×10−6Ω·cm), is higher than that of Cu, and signal delay or power loss, which is caused due to the interconnection resistance, become problematic.
On the other hand, when attention is paid to an interconnection structure of a TFT substrate including an oxide semiconductor layer, at present, an interconnection structure shown in FIG. 3 (which will be hereinafter sometimes referred to as “conventional structure” for the sake of convenience) is used as the structure of TFT for many purposes. In FIG. 3, a gate electrode, a gate insulating film, an oxide semiconductor film, and a source-drain electrode are formed in this order from the side of the substrate, and a metal electrode such as the source-drain electrode is formed on an upper layer of IGZO. The semiconductor device described in the above-described Patent Document 1 also includes this conventional structure. While FIG. 3 illustrates an example of a “bottom gate type” in which the gate electrode is located in a lower side, a “top gate type” in which the gate electrode is located in an upper side is also encompassed. Also, in the case of using an oxide semiconductor, a silicon oxide film or silicon oxynitride film is frequently used as the gate insulating film instead of silicon nitride film. This is because in the oxide semiconductor, its excellent properties are lost under a reducing atmosphere, and therefore, the use of silicon oxide (silicon oxynitride) capable of undergoing deposition under an oxidizing atmosphere is recommended.
But, the TFT substrate of the conventional structure using an oxide semiconductor such as IGZO involves the following problems. First of all, when forming an interconnection pattern by undergoing wet etching of a metal electrode (Cu based interconnection material), such as a source-drain electrode formed on an upper layer of IGZO, with the use of the acidic etching solution or the like, there is no etching selection ratio between IGZO and the Cu based interconnection material (in other words, the etching selectivity that only the Cu based interconnection material as the upper layer is selectively etched, but IGZO as the lower layer is not etched is small), and therefore, there is a problem that even the IGZO locating in the lower is damaged by etching. As a countermeasure thereto, for example, there is a proposed method of providing an etch stopper layer as a protective layer on a channel layer of IGZO. However, the steps become complicated, resulting in an increase of manufacturing costs. Secondly, the foregoing conventional structure involves a problem that when a heat history of about 250° C. or higher is applied, the contact resistance between the source-drain electrode and the oxide conductor increases. As for this issue, when a high melting point metal such as Ti is intervened, the increase of the contact resistance is suppressed. However, as described above, from the viewpoints of costs and productivity, an omission of the high melting point metal (barrier metal layer) is eagerly desired. Also, though Ti is deposited by means of dry etching using a plasma, it is difficult to apply them to interconnection materials which are hardly subjected to dry etching, such as Cu.
Then, in recent years, there is a proposed interconnection structure shown in FIG. 1 or 2 (which will be hereinafter sometimes referred to as “structure of the invention” for the sake of convenience for the purpose of being distinguished from the conventional structure of FIG. 3) in which the order of the oxide semiconductor film and the source-drain electrode is reverse to that of the conventional structure of FIG. 3 (for example, Non-Patent Document 1). This has a structure in which a gate electrode, a gate insulating film, a source-drain electrode, and an oxide semiconductor film are formed in this order from the side of the substrate. As shown in FIG. 1 or 2, an oxide semiconductor and a transparent conductive film (ITO in the drawings) which constitutes a pixel electrode are located on substantially the same plane as an interconnection material constituting the source-drain. While FIG. 1 or 2 illustrates an example of a “bottom gate type” in which the gate electrode is located in a lower side, a “top gate type” in which the gate electrode is located in an upper side is also encompassed, similar to the conventional structure shown in the above-described FIG. 3.
It may be considered that when the structure of the invention shown in FIG. 1 or 2 is adopted, the problems which the conventional structure of the above-described FIG. 3 involves can be dissolved. However, according to the structure of the invention, in the case where different materials, e.g. a high melting point metal (barrier metal layer) such as Ti and Mo, and pure Cu, etc. are laminated, there is a possibility that the contact resistance with the oxide semiconductor is different, and therefore, there is a problem that an effective channel length is not easily determined. That is, when a high melting point metal such as Ti and Mo is intervened above and below pure Cu, in the case where the contact resistance between Ti or Mo and the oxide semiconductor is larger than the value with pure Cu, or in the reverse case thereto, there is a problem that it is difficult to determine with ease which current is decided as the effective channel length between the current flowing source-drain electrode and the current flowing IGZO. Also, the above-described Non-Patent Document 1 discloses an interconnection structure in which Al is used as an interconnection material of the source-train interconnection, and Ti is intervened above and below the Al. However, the structure of the invention using, as the interconnection material, Cu having an electrical resistivity lower than Al has not been disclosed up to date.
Now, in TFT substrates using an oxide semiconductor represented by IGZO or the like, a single layer of Mo or Ti, or a laminated material in which a high melting point metal (barrier metal layer) such as Ti and Mo is intervened above and/or below pure Al or an Al alloy such as A—Nd (these will be hereinafter sometimes summarized and referred to as “Al based alloy”) is mainly used as an interconnection material such as a gate interconnection and a source-drain interconnection. The Al-based alloy is adopted for the reasons that the electrical resistance is small, and micromachining is easily performed, and the like. Also, a main reason of using a high melting point metal for the interconnection material resides in the matter that Al is very easily oxidized, so that when the Al based alloy interconnection is connected directly to the oxide semiconductor layer, an insulating layer of high-resistance Al oxide is formed at an interface between the Al based alloy interconnection and the oxide semiconductor layer by oxygen generated in a deposition process of a liquid crystal display, oxygen added during the deposition, or the like, whereby the connection resistance to the oxide semiconductor layer (contact resistance) increases, and the display quality of a screen is lowered. However, the use of the high melting point metal brings about an increase of the costs or a lowering of the productivity, and therefore, taking mass production of a liquid crystal display into consideration, an omission of the high melting point metal is desired. That is, it is desirable to provide a novel interconnection material capable of reducing the contact resistance, even if the barrier metal layer is omitted to connect the Al based alloyed interconnection directly to the oxide conductor layer.
On the other hand, when attention is paid to an interconnection structure of a TFT substrate including an oxide semiconductor layer, at present, an interconnection structure shown in FIG. 5 (which will be hereinafter sometimes referred to as “conventional structure” for the sake of convenience) is used as the structure of TFT for many purposes. In FIG. 5, a gate electrode, a gate insulating film, a semiconductor film, and a source-drain electrode are formed in this order from the side of the substrate. While FIG. 5 illustrates an example of a “bottom gate type” in which the gate electrode is located in a lower side, a “top gate type” in which the gate electrode is located in an upper side also encompassed. Also, in the case of using an oxide semiconductor, SiO2 or SiON is frequently used as the gate insulating film instead of SiN film. This is because in the oxide semiconductor, its excellent properties are lost under a reducing atmosphere, and therefore, the use of SiO2 (SiON) capable of undergoing deposition under an oxidizing atmosphere is recommended.
But, the TFT substrate of the conventional structure using an oxide semiconductor such as IGZO involves the following problems. First of all, when forming an interconnection pattern by undergoing wet etching of a metal electrode (Al based interconnection material), such as a source-drain electrode formed on an upper layer of IGZO, with the use of the acidic etching solution, there is no etching selection ratio between IGZO and the Al based interconnection material (in other words, the etching selectivity that only the Al based interconnection material as the upper layer is selectively etched, but IGZO as the lower layer is not etched, is small), and therefore, there is a problem that even the IGZO locating in the lower is damaged by etching. As a countermeasure thereto, for example, there is a proposed method of providing an etch stopper layer as a protective layer on a channel layer of IGZO. However, the steps become complicated, resulting in an increase of manufacturing costs. Secondly, the foregoing conventional structure involves a problem that when a heat history of about 250° C. or higher is applied, the contact resistance between the source-drain electrode and the oxide conductor increases. As for this issue, when a high melting point metal such as Ti is intervened, the increase of the contact resistance is suppressed. However, as described above, from the viewpoints of costs and productivity, an omission of the high melting point metal (barrier metal layer) is eagerly desired. Also, though Ti is deposited by means of dry etching using a plasma, it is difficult to apply them to interconnection materials which are hardly subjected to dry etching, such as Cu.
Then, in recent years, there is a proposed interconnection structure shown in FIG. 4 (which will be hereinafter sometimes referred to as “structure of the invention” for the sake of convenience for the purpose of being distinguished from the conventional structure of FIG. 5) in which the order of the oxide semiconductor film and the source-drain electrode is reverse to that of the conventional structure of FIG. 5. This has a structure in which a gate electrode, a gate insulating film, a source-drain electrode, and an oxide semiconductor film are formed in this order from the side of the substrate. As shown in FIG. 4, an oxide semiconductor and a transparent conductive film (ITO in the drawing) which constitutes a pixel electrode are located on substantially the same plane as an interconnection material constituting the source-drain. While FIG. 4 illustrates an example of a “bottom gate type” in which the gate electrode is located in a lower side, a “top gate type” in which the gate electrode is located in an upper side is also encompassed, similar to the conventional structure shown in the above-described FIG. 5.
It may be considered that when the structure of the invention shown in FIG. 4 is adopted, the problems which the conventional structure of the above-described FIG. 5 involves can be dissolved. However, according to the structure of the invention, in the case where a high melting point metal (barrier metal layer), such as Ti and Mo, is intervened in a material which is not able to come into direct contact with the oxide semiconductor, such as pure Al, there is a problem that an effective channel length is not determined. That is, when a high melting point metal such as Ti and Mo is intervened above and below the pure Al, pure Al and IGZO cannot be electrically connected to each other, and therefore, there is a problem that it is difficult to determine with ease which current is decided as the effective channel length between the current flowing source-drain electrode and the current flowing IGZO (for example, the upper side and the lower side).